What Is A Four Bit Register

Module 5.vii

Registers

After studying this section, yous should be able to:
Understand the operation of digital parallel in/parallel out (PIPO) registers.
Describe the action of serial and parallel shift registers.
• Series in/Serial out (SISO).
• Serial in/Parallel out (SIPO).
• Parallel in/Serial out PISO.
Understand the operation of reversible shift registers.
Recognise common features used in shift annals ICs.
Utilise Software to analyse the operation of shift registers.

Parallel In - Parallel Out (PIPO) Registers

Fig. 5.7.1 Parallel In/Parallel Out (PIPO) Annals

An electronic annals is a form of memory that uses a series of flip-flops to store the individual bits of a binary word, such as a byte (8 bits) of information. The length of the stored binary word depends on the number of flip-flops that make upward the register. A simple 4-bit register is illustrated in Fig. 5.seven.1 and consists of four D Type flip-flops, sharing a common clock input, providing synchronous operation ensuring all $.25 are stored at exactly the aforementioned time.

The binary give-and-take to be stored is practical to the four D inputs and is remembered by the flip-flops at the ascent edge of the next clock (CK) pulse. The stored information can then exist read from the Q outputs at whatever time, equally long as power is maintained, or until a change of data on the D inputs is stored by a farther clock pulse, which overwrites the previous data.

Different types of register are generally classified past the method of storage and readout used; this basic form of register is therefore classified as a 'Parallel In/Parallel Out' (PIPO) register.

Shift Registers.

Shift registers have a similar structure to the PIPO annals only have the added ability to shift the stored binary discussion left or correct, one bit at a time. This makes them extremely useful for many applications. They are used in handling serial data and converting it to parallel form or back again to series form, and therefore are an essential component in advice systems. Shift registers are also essential in arithmetics circuits where binary numbers may be shifted right (and then divided by two), or left (multiplied by two) as part of a calculation. Shift registers tin be used to delay the passage of data at a particular indicate in a circuit. As the data is shifted ane bit at a time from input to output, the corporeality of filibuster will depend on the number of flip-flops in the annals and the frequency of the clock pulses driving the shift annals. Because a number of serial bits of data are stored as they enter the input, and are so recovered from the output at some later time, this action can likewise be described as a serial retentivity, or as a digital delay line.

Fig. 5.vii.2 Series In/Serial Out (SISO) Shift Register

The elementary storage register shown in Fig. v.7.one can exist modified to a shift register by connecting the output of ane flip-flop into the input of the next, equally shown in Fig. v.seven.2. The basis of shift annals circuits is the D-blazon flip-flop, but the clocked SR or the JK flip-flop may also be converted to D-types by the inclusion of an inverter between Southward and R or between J and K. In all cases the clock input is in synchronous fashion.

The serial input of the shift register in Fig. five.7.2 is the D input of the first flip-flop, and the serial output is the Q output of the terminal flip-flop in the chain. The logic land at the serial input appears at the output, a number of clock pulses (equal to the number of flip flops) later.

Fig. 5.7.3 Timing Diagram and State Tabular array for SISO Operation

Modes of Shift Register Operation.

SISO

A State Tabular array and Timing Diagram illustrating the operation of Fig.5.7.2 is shown in Fig. v.seven.3 where the timing diagram shows the fourth dimension relationship between the CK pulses and changes at the Q outputs of the circuit. Information technology can be seen that if the serial input goes from 0 to 1 just before CK pulse 1, the Q output of flip-flop FF0 will go high at the rising edge of CK pulse 1. At the adjacent clock pulse rising border, the logic 1 will be transferred to FF1 and then on until it reaches FF3, and the series output.

The aforementioned action can also be illustrated past a State Table, which, rather than showing timing data, shows the states of the four Q outputs after each clock pulse. After each CK pulse one more flip-flop output is set to i until, subsequently 4 pulses, cavalcade 4 shows that all Q outputs, including the serial output, are at logic 1. This form of operation is chosen 'serial in/serial out' or SISO.

SIPO

Fig. 5.7.iv Serial In/Parallel Out (SISO/SIPO) Shift Annals

In Fig. 5.7.four the shift annals is modified to include additional Q outputs from each flip-bomb, so allowing the register to input serial information, and output it in both series and parallel course. The register could therefore now be called both a 'Series In/Serial Out and Series In/Parallel Out' (SISO/SIPO) register. This format is the basis for converting serial data to parallel data.

PISO

Fig. five.7.5 Multiple Style (SISO, SIPO, PISO, PIPO) Shift Register

If use is also made of the Q output, and the boosted preset (PR) and clear (CLR) inputs bachelor on many flip-flops, the shift register could be made more versatile all the same.

Fig. 5.seven.5 shows a shift annals modified to enable it to be loaded with a four-scrap parallel number, which may then be shifted right to appear at the serial output one bit at a time. As the 'Parallel In/Serial Out' or PISO register as well has a series input, it can besides be used as a SISO register, and if extra outputs from each Q output were also included, the register would also have Serial In/Parallel Out (SIPO) operation.

Loading Parallel Data

If the LOAD input is taken to logic 0, the LOAD control line connected to the iv pairs of NAND gates associated with the four flip-flops will be at logic 1, and all four pairs of NAND gates volition be enabled. Therefore a logic i appearing on any of the D inputs will be inverted by the NOT gate connected to the D input, making the inputs to the left mitt NAND gate of the relevant pair of gates, logic i and logic 0. This will cause logic 1 to be applied to the CLR input of the flip-flop.

The right manus NAND gate of the pair will take both inputs at logic 1, due to the logic i on LOAD line and logic 1 on the D input, then will output logic 0 (NAND gate rules) to the PR input of the flip-flop, setting the Q output to logic 1.

If the D input is at logic 0, the left manus gate of the NAND gate pair will output logic 0 and the right hand NAND gate will output logic 1, causing the CLR input to clear the Q output of the relevant flip-bomb to logic 0.

Detect that as JK flip-flops are beingness used in this design, a NOT gate is connected betwixt J and K of the starting time flip-bomb of the chain to make the JK flip-bomb mimic a D Blazon. The remaining flip-flops of the shift register accept J and Thou continued to the previous Q and Q outputs, then will too exist at opposite logic states.

A four-bit reversible shift register.

The shift register in Fig five.vii.v could be operated as:

A parallel in/parallel out register. (PIPO)
A Serial in/serial out register. (SISO)
A series in/parallel out annals. (SIPO)
A parallel in/serial out annals. (PISO)

However Fig 5.7.5 can only shift information in one direction, i.e. left to right. To be truly versatile information technology could be an reward to be able to shift data in both directions and in any of the four shift register operating modes. Fig. 5.7.6 achieves this by adding data steering circuitry.

Fig. v.7.six iv-Bit Reversible PIPO/PISO/SISO/SIPO Shift Annals

The gating system at the lesser of Fig 5.7.6 (gates G1 to G13) is exactly the aforementioned equally that described above in Fig. v.7.5, and these gates command the loading of parallel information.

Gates G14 to G28 in Fig v.7.6 command the direction of information flow through the register. The JK flip-flops use the inverter gates G29 to G32 to ensure that J and K are at opposite logic states, so the flip-flops are mimicking D Type operation, with J being used as the data input. Find also that the clock is connected in the familiar synchronous mode.

Operation.

In any of the modes involving series functioning, information may be shifted left or shifted right by the application of a suitable logic level at the shift control (R/L) input.

With a logic 1 at this input the annals is in the shift correct mode, and data is taken into the 'Series in R' input to be shifted right by application of successive clock pulses, appearing as parallel data, changing with each clock pulse, on the flip flop Q outputs. After four clock pulses the data begins to announced in serial form on the Q₃ output, which is besides the 'Series Out R' output.

The logic i on the shift control (R/L) enables gates G18, 20, 22 & 24, but because the logic 1 is inverted past G27, gates G19, 21, 23 & 25 are disabled.

The path of serial information (e.k. a logic ane) from left to right is as follows; the logic i actualization at the input to G26 is inverted and passes through G18 which re-inverts it to logic one and, as G19 is disabled its output must as well be at logic 1. Both inputs to the AND gate G14 are at logic 1 and therefore and then is its output, (AND gate rules) making the J input of FF0 logic ane.

On the arrival of a clock pulse, the logic one input to FF0 will appear on the output Q₀. Its changed (logic 0) will also appear on the Q output of FF0. This logic 0 forms the input to the next multiplexer arrangement, gates G20, 21 & 15. As G20 is enabled (and G21 disabled) the logic 0 becomes logic i at G15 output and so is fed to the J input of FF1. This method is used to transfer information to each flip-flop in the chain.

To accomplish shift left operation, the shift command (R/L) is set to logic 0 and then enables gates G19, 21, 23 & 25 while disabling gates G18, 20, 22 & 24. Therefore the Q output of FF3 is continued via G23 and G16 to the D input of FF2, the Q output of FF2 is connected to the J input of FF1 via G21 and G15 (remember that G24 is disabled, then FF3 is isolated from this path). Finally, the Q output of FF1 is connected via G19 and G14 to the J input of FF0, the Q₀ output of which is also the 'Serial Out L' output. The ability to shift information in either direction, together with the parallel input and output facilities make this register a very versatile device.

It is common to connect shift register ICs in cascade, using the serial output of i annals to connect to the serial input of the next register in the chain. For this reason both the data and clock inputs and outputs of register ICs are normally buffered.

Some examples from the many commercially available IC registers using these and similar methods, available in both CMOS and TTL versions, are listed below.

74HC164 8-Bit SIPO Shift register from NXP
74HC594 viii-Flake SIPO/SISO with PIPO output storage register and dual clocks - from NXP.
74HC595 8-Bit SIPO/SISO with tri-state output PIPO storage register and dual clocks - from NXP.
HEF4014B PISO Register with 8-bit synchronous parallel LOAD and outputs from Q5, Q6 & Q7 only - from NXP.
CD4031B 64 Stage SISO shift register with re-apportionment mode - from Texas Instruments.